1. Technical Field
The present invention relates in general to data processing and, in particular, to a processor and method of performing load operations in a processor. Still more particularly, the present invention relates to a processor and method of processing a load instruction that bifurcate load execution into two separate operations.
2. Description of the Related Art
Most processors' instruction set architectures (ISAs) include a load or similar type of instruction that, when executed, causes the processor to load specified data from memory (e.g., cache memory or system memory) into the processor's internal registers. Conventional processors handle the execution of load instructions in one of two ways. First, a processor may execute load instructions strictly in program order. In general, the execution of load instructions with strict adherence to program order is viewed as disadvantageous given the fact that at least some percentage of data specified by load instructions will not be present in the processor's cache. In such cases, the processor must stall the execution of the instructions following the load until the data specified by the load is retrieved from memory.
Alternatively, a processor may permit load instructions to execute out-of-order with respect to the programmed sequence of instructions. In general, out-of-order execution of load instructions is viewed as advantageous since operands required for execution are obtained from memory as soon as possible, thereby improving overall processor throughput. However, supporting out-of-order execution of load instructions entails additional complexity in the processor's architecture since, to guarantee correctness, the processor must be able to detect and cancel an out-of-order load instruction that loads data from a memory location targeted by a later-executed store instruction (executed in the same or a remote processor) preceding the load instruction in program order.